Intel Architecture 64 (IA-64)

In 1999, Intel plans to ship its new processor, code name Merced, the first microprocessor that is based on a next generation architecture. Known as Intel Architecture-64 (IA-64), it is something which is claimed to be completely different. It is a forward looking architecture that uses long instruction words (LIW), instruction predication, branch elimination, speculative loading and other advanced techniques to extract more parallelism from program code.

Intel's next generation 64-bit Merced processor is part of the IA-64 line developed by Intel and technology partner HP. As a hybrid of Intel's x86 technology and HP's PA-RISC chip, Merced will combine the benefits of RISC and CISC to offer Explicitly Parallel Instruction Computing (EPIC).

The new IA-64 bit architecture relies on a new kind of cooperation between hardware and compiler. IA-64's most notable characteristic is its massive complement registers. There are 128 integer, 128 floating-point and 64 new speculative registers for the compiler to work with. This aids performance by obviating the need for the compiler to perform bulky register renaming tasks.

Another important feature of IA-64 is its very long instruction word (VLIW) architecture. A packed instruction word, which is 128 bits wide, incorporates three separate instructions and maps them to functional units in the target processor. A template field specifies dependencies between the instructions and other packed words.

With EPIC, instead of generating machine instructions sequentially and then letting the processor decide on how to execute them, the compiler produces code that explicitly tells the CPU which instruction it can execute in parallel. The parallelized instructions allow the chip to process a number of instructions simultaneously, theoretically making IA-64 chips more efficient.

The new chip also offers backward compatibility, in the sense that it will also read the 32-bit code that is used by the current generation of Intel processors. That promises far better 32-bit performance than can be obtained using the alternative software translation.

Asynchronous Transfer Mode

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Last Updated 24th January 1998